refer to Operating Rules #10 in this datasheet. Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering. Part Number: 74LS, Maunfacturer: National Semiconductor, Part Family: 74, File type: PDF, Document: Datasheet – semiconductor. 74LS datasheet, 74LS pdf, 74LS data sheet, datasheet, data sheet, pdf, Fairchild Semiconductor, Dual Non-Retriggerable One-Shot with Clear and.

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Input Current Max Input Catasheet. Pulse width is defined by the relationship: To obtain the best and trouble free operation from. This CLR input also serves as a trigger input when it is pulsed with a low level pulse transition.

DescriptionThe absolute maximum darasheet of the 74LS00N are: Pin A is an active-LOW trigger transition input and. I CC Supply Current. The pin-out is identical to DM74LS but, functionally it is not.

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Each multivibrator of the 74LS features a negative-transition-triggered input and a positive-transition-triggered input either of which can be used as an dataasheet input. This provides the input with. SeekIC only pays the seller after confirming you have received your order.


Pulse triggering occurs at a voltage level and is not related to the transition time of the input pulse. Recent History What is this? Additionally datashest internal latching circuit at the input stage also provides a high immunity to V CC noise. The DM74LS is a dual monostable multivibrator with. The clear CLR input can terminate the output.

Motorola 74LS Series Datasheets. 74LSN, SN54LS Datasheet.

Each device has three inputs permit. Jitter-free operation is maintained over the full temperature and VCC ranges for greater than six decades of timing capacitance 10 pF to 10 mFand greater than one decade of timing resistance 2.

I OS Short Circuit. To obtain the best and trouble free operation from this device please read operating rules as well as the Fair- child Semiconductor one-shot application notes carefully and observe recommendations. Devices also available in 74lss221 and Reel.

A high immunity to VCC noise is also provided by internal latching circuitry. Order Number Package Number.

74LS221 PDF Datasheet浏览和下载

dattasheet Input pulse width may be of any duration relative to the output pulse width. Margin,quality,low-cost products with low minimum orders. Output pulse width may be varied from 35 nanoseconds to a maximum of 70 s by choosing appropriate timing components. In most applications, pulse stability will only be limited by the accuracy of external timing components.


74LS Datasheet(PDF) – Fairchild Semiconductor

Not more than one output should be shorted at a time, and the duration should not exceed one second. Additionally an internal latching. This mode of triggering requires first the B input be set from a. When you place an order, your payment is made to SeekIC and not to your seller. You may also be interested in: This CLR input also serves as a trigger.

Faithfully describe 24 hours delivery 7 days Changing or Refunding. Output rise and fall times are independent of pulse length. If pulse cutoff is not critical, capacitance up to mF and resistance as low as 7ls221. V I Input Clamp Voltage. The range of jitter-free pulse widths is extended if VCC is 5.

The output pulses can be terminated by the overriding clear. Each device has three inputs permit- ting the choice of either leading-edge or trailing-edge trig- gering. This provides the input with excellent noise immunity. Freight and Payment Recommended logistics Recommended bank.

Please create an account or Sign in. The clear CLR input can terminate the output pulse at a predetermined 74lz221 independent of the timing components.